Serial (not parallel) transmission

In most of the projects, we get to the point where we need to transmit data – either the input as the output. They can be transferred in serial (bit by bit in one line) or parallel mode (multiple bits at once using multiple lines). In this post, we will talk about serial transmission as it’s more popular in common world. Mainly because it uses fewer wires compared to parallel transmission and it’s more immune to signal noise. And when we talk about sending tens of Gigabits of data – it makes a huge difference.

It’s (mainly) about the speed

Even simplest microcontrollers have some serial communication interfaces embedded in hardware – UART, SPI, 1-Wire, I2C are just some of the acronyms you may have heard. These are fairly slow with maximum speed below 100 Mb/s (yes, when we speak about communication in FPGA, these speeds are slow…), so they can be easily implemented using common pins. The real advantage of FPGA is visible when we need much faster transfers. How fast? Well, in Virtex UltraScale+ from Xilinx you can find line rates up to 58Gb/s and combine more of these can give bandwidth measured in Terabits per second.

Interfaces, transceivers

We don’t always need such speed. Also, not every project needs such a big chip for it. That’s why we can choose a chip that fits our needs – each family of devices has got different transceivers in it (check the table below). So what transceivers and what speeds are available? Let’s start with some common interfaces in processor side (PS) of Zynq 7000/Zynq MPSoC.

 

Chip FamilyInterfaces
Zynq 70002 x UART, 2 x CAN 2.0B, 2 x I2C, 2 x SPI, 2 x USB 2.0 (OTG), 2 10/100/1000 Ethernet, 2 x SD/SDIO
ZYNQ MPSoC UltraScale+2xUSB 2.0, 2x SD/SDIO, 2x UART, 2x CAN 2.0B, 2x I2C, 2x SPI, PCIe Gen2 x4, 2x USB3.0, SATA 3.1, DisplayPort, 4x 10/100/1000 Ethernet, SATA 3.1

 

Some interfaces are available as integrated (hardware) IP in programmable logic (PL) of FPGA. Keep in mind that some packages of the same chip family can have transceivers with different speed.

 

Transceivers in Xilinx FPGAs

Chip familytransceiver nameintegrated IPspeed [Gb/s]
Virtex UltraScale+GTY/GTMPCIe Gen3/4, 150G Interlaken, 100G Ethernet w/ KR4 RS-FEC, CCIX 32.75/58.0
Kintex UltraScale+GTH/GTY [1]PCIe Gen3/4, 150G Interlaken, 100G Ethernet w/ RS-FEC16.3/32.75
Zynq UltraScale+ GTH/GTY PCIe Gen3/4, 150G Interlaken, 100G Ethernet MAC/PCS w/ RS-FEC 16.3/32.75
Virtex UltraScaleGTH/GTY PCIe Gen1/2/3, Interlaken, 100G Ethernet16.3/30.5
Kintex UltraScaleGTH [2]PCIe Gen1/2/3, Interlaken, 100G Ethernet16.3
Virtex-7 GTX/GTH/GTZPCIe Gen2 (Gen3 Soft IP)12.5/13.1/28.05
Kintex-7 GTX [3]PCIe Gen212.5
Artix-7GTPPCIe Gen1/26.6
Zynq-7000GTXPCIe Gen212.5
Spartan-6GTPEndpoint PCIe v1.1 - 1lane3.2

 

1. GTY transceiver line rates are package limited: B784 to 12.5 Gb/s; A676, D900, and A1156 to 16.3 Gb/s [Source]

2. GTH transceivers in A784, A676, and A900 packages support data rates up to 12.5Gb/s.GTY transceivers in KU095 devices support data rates up to 16.3Gb/s. [Source]

3. GTX transceivers in FB packages support the following maximum data rates: 10.3Gb/s in FBG484; 6.6Gb/s in FBG676 and FBG900. [Source]